1. Field of the Invention
The present invention relates generally to a method for preventing circuit failures due to gate oxide leakage, and more particularly pertains to a methodology for efficiently checking many nets of a circuit on a chip or within a macro to find logical fails due to gate oxide leakage using DC calculations, wherein the gate leakage is treated as a noise source in a static noise analysis of the circuit.
2. Discussion of the Prior Art
As gate oxides on field effect transistors (FETs) have scaled to thinner dimensions, the occurrence of gate tunneling current due to gate oxide leakage has become more prevalent. Circuits with a large fanout (feeding and serving as an input to many downstream circuits) or with a large series resistance may not be able to provide a sufficiently large gate current at each receiving circuit and can cause an increase in crossover current and possibly a fail.